As is well known, memory devices usually include sense amplifiers of either the register or latch type, that is, circuits which are capable of reading data from a memory and retaining it for a given time period.
A known type of sense amplifier SA is depicted in FIG. 1. The sense amplifier SA comprises a latch circuit LA placed between a supply voltage reference Vdd and an internal circuit node X. The latch circuit LA has first IN1' and second IN2' input terminals, as well as first OUT.sub.- L and second OUT.sub.- R output terminals, respectively connected to first M1 and second Mr memory cells.
In fact, the sense amplifier SA is commonly used for reading from memory cells M1, the contents whereof are compared to those of reference memory cells Mr, specifically non-programmed or "virgin" cells.
Accordingly, the sense amplifier SA basically comprises a read leg RR1, which is taken to the memory cell M1 and has a read current I1 flowed therethrough, and a reference leg RRr, which is taken to the reference memory cell Mr and has a reference current Ir flowed therethrough. Both legs RR1 and RRr are connected to the latch circuit LA.
In addition, the latch circuit LA comprises first Tp1 and second Tn1 read transistors which are connected, in series with each other, between the supply voltage reference Vdd and the internal circuit node X and have their control terminals connected together and to the second output terminal OUT.sub.- R.
In the embodiment shown in FIG. 1, the first read transistor Tp1 is a p-channel MOS transistor, or PMOS transistor, while the second read transistor Tn1 is an n-channel MOS transistor, or NMOS transistor.
Similarly, the latch circuit LA comprises first Tpr and second Tnr reference transistors which are connected, in series with each other, between the supply voltage reference Vdd and the circuit node X, and have their control terminals connected together and to the first output terminal OUT.sub.- L.
In the embodiment shown in FIG. 1, the first reference transistor Tpr is a PMOS transistor, and the second reference transistor Tnr is an NMOS transistor.
Furthermore, the first OUT.sub.- L and second OUT.sub.- R output terminals are respectively connected to the common drain terminals of the read transistors Tp1, Tn1 and of the reference transistors Tpr, Tnr, as well as to the supply voltage reference Vdd via first Tpc1 and second Tpcr control transistors. These control transistors are, in turn, connected between said output terminals OUT.sub.- L, OUT.sub.- R and the supply voltage reference Vdd and have their control terminals connected to the first IN1' and second IN2' input terminals of the latch circuit LA.
In particular, the control transistors Tpc1 and Tpcr are PMOS transistors.
The sense amplifier SA further comprises an equalization block BE which is connected between the first OUT.sub.- L and second OUT.sub.- R output terminals and connected to the circuit node X, the latter having an equalization signal EQ present thereon. This equalization block BE is operative to prevent unbalance between the voltages at the output terminals OUT.sub.- L and OUT.sub.- R.
The sense amplifier SA has positive feedback between the aforesaid output terminals OUT.sub.- L and OUT.sub.- R. Hence, the equalization of the output terminals OUT.sub.- L and OUT.sub.- R needs to be as accurate as possible, since any unbalance between the voltages presented at such terminals would have irreparable consequences on the operation of the sense amplifier SA.
Lack of equalization would indeed result in a situation of bistability of the latch circuit, with a consequent risk of altered reading. In particular, the condition of perfect equalization should be achieved at the pre-reading stage.
The equalization block BE of the sense amplifier SA of FIG. 1 basically comprises an NMOS transistor Tne.
It should be noted that the required equalization function cannot be obtained from a PMOS transistor due to the presence of capacitive couplings (tied to Miller's capacitance) introducing a disturbance which could overlay the useful signal.
While offering a number of advantageous features, such as modulability of the sense amplifier SA gain, this prior art solution based on the use of NMOS-type transistors is still beset with a number of problems, especially operating at high voltages.
In fact, the threshold value of the equalization transistor Tne rises due to the so-called "body effect". This rise does not present a problem at low voltages (where the threshold voltage of the transistor Tne goes from 0.4 to 0.6 V), but becomes objectionable at high voltages (where the threshold voltage of the transistor Tne goes from 0.4 to 1-1.5 V), approaching the working point of the latch circuit LA, which has a quite high working point due to the presence of the PMOS transistors Tp1 and Tpr. Actually, these transistors Tp1 and Tpr must be highly conductive in order to rapidly precharge the latch circuit LA, this being a vital function to a correct reading.
By setting a high working point for the sense amplifier SA, the use of highly conductive transistors results in poor equalization of the whole circuit in conjunction with the aforesaid "body effect".
The equalization signal EQ is also effective to catch data, thereby allowing the sensitivity of the sense amplifier SA to be adjusted by modulating its slope. Thus, for circuits which employ sense amplifiers of the latching type, an effective equalization of the output terminals of the latch circuit is essential. Also valuable is the ability to modify the equalization conditions in a "gradual" manner, so as to reduce disturbances due to parasitic couplings (referred to as "Miller's Effect" in the literature), and especially to build a signal which, albeit weak, can be detected reliably and stored correctly.
Accordingly, it is important to situate the appropriate moment for a quick and accurate capture of given data. This moment must be preceded by an absolutely perfect equalization and be as immediate as possible with respect to the reading operations, so as to avoid a time-consuming initial step of building up the output signal from the sense amplifier, which is liable to lengthen the reading time considerably.